(1) Field of the Invention
The present invention relates to the manufacture of flash-EEPROM cells (Electrically Erasable Programmable Read Only Memories), and in particular, to multi-layer spacer technology for flash-EEPROMs.
(2) Description of the Related Art
In floating gate memory devices including electrically erasable and electrically programmable read-only memories (EEPROMs) or flash EEPROMs, the source and drain regions are usually aligned to the floating gate or to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is formed which is usually separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. The spacing between the select and control gates can be reduced, and hence the memory cell size decreased, by forming a split-gate where the source and drain regions are aligned to a spacer formed after the floating gate is formed. However, the integrity of the spacer technology must be such that the amount of alignment overlap or offset between the floating gate and source and drain regions are precise so as to not degrade the programming and erasing performance of the memory cell.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1a. Here, a MOS transistor is formed on substrate (10) and has a channel (20) defined by source (30) and drain(35), a floating gate (50) to which there is no direct electrical connection and a control gate (70) with a direct electrical connection. The floating gate is separated from the substrate by a thin layer of gate oxide (40) while the control gate is generally positioned over the floating gate with tunnel oxide and an interpoly dielectric therebetween, usually formed of oxide/nitride/oxide (ONO) composite film (60). In the structure shown in FIG. 1a, control gate (70) overlaps the channel region, (21), adjacent to the channel (20) under the floating gate, (50). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (21) determines the cell performance. Therefore, it is important as to how the transistor and gate length are defined, and nitride spacers, not shown in FIG. 1a, but disclosed in the embodiments of this invention later, can be used effectively for the purposes of precisely defining such cell parameters.
To program the transistor shown in FIG. 1a, charge is transferred from substrate (10) through gate oxide (40) and is stored on floating gate (50) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d of xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (30) and drain (35), and to control gate (70), and then sensing the amount of charge on floating gate (50). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of critical importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate Fowler-Nordheim tunneling.
In the conventional memory cell shown in FIG. 1a, word lines (not shown) are connected to control gate (70) of the MOS transistor, while the length of the MOS transistor itself is defined by the source (30) drain (35) N+ regions shown in the same Figure. As is well known by those skilled in the art, the transistor channel is defined by masking the N+ regions. However, the channel length of the transistor varies depending upon the alignment of the floating gate (50) with the source and drain regions. This introduces significant variations in cell performance from die to die and from wafer to wafer. Furthermore, the uncertainty in the final position of the N+ regions causes variations in the series resistance of the bit lines connected to those regions, and hence additional variation in the cell performance. Finally, in order to insure that the resistance of the bit line is acceptably low, the bit lines over the N+ regions are formed wider than the required minimum, thereby giving rise to an increase in the overall area of the cell.
To overcome some of the problems cited above, Manley in U.S. Pat. No. 5,115,288 teaches a method that utilizes a conductive polysilicon spacer to define the gate length of the series transistor in a split-gate memory cell. The spacer is shown with reference numeral (80) in FIG. 1b. The memory cell of FIG. 1b is formed essentially in the same way the cell of FIG. 1a is formed except that after forming of the interpoly layer (60) and following well-known methods, a polysilicon spacer is formed adjacent to one of the opposing sides of the floating gate (50), as described in the same U.S. Pat. No. 5,115,288. The conductive spacer is insulated from the floating gate by the interpoly layer (60). Next, the spacer is utilized to define a self-aligned source region (30) while the floating gate is utilized in the self-aligned definition of the drain region (35). This process results in the floating gate extending only over a portion of the channel region in the manner of a conventional split-gate cell, and with the spacer being positioned over the remaining portion (21) of the channel between the floating gate and the source region. A conductive polysilicon control gate (70) is then formed in electrical contact with the polysilicon conductive spacer. As seen in FIG. 1b, control gate (70) extends over floating gate (50), but is electrically insulated from the floating gate by the interpoly layer (60). The length of the polysilicon spacer (80) so formed can, be controlled so as to eliminate the misalignment problems associated with conventional split-gate cells.
In U.S. Pat. No. 5,633,184, Tamura, et al., show a method of forming a spacer under the floating gate. In U.S. Pat. No. 5,554,869, Chang uses two different spacers on the sides of the control gate in order to control the degree of misalignment in forming an EEPROM. In U.S. Pat. No. 5,045,486, on the other hand, Chittipeddi, et al., teach a method of preventing channeling during implantation through a gate in the fabrication of transistors in US. This invention discloses a more precise way of controlling the size and shape of spacers and hence, that of cell alignment, by employing multi-layer spacers in the manufacture of flash EEPROMs.
It is therefore an object of this invention to provide a method of forming multi-layer spacers (MLS) in the manufacture of flash EEPROMs.
It is another object of this invention to provide a method of etching multi-layer spacers in the manufacture of flash EEPROMs.
It is yet another object of this invention to provide a method of improving alignment between floating gate and impurity regions in the semiconductor substrate by employing MLS.
These objects are accomplished by providing a semiconductor substrate having a gate oxide layer formed thereon; forming a first polysilicon layer over said gate oxide layer; forming a mask layer over said first polysilicon layer; patterning said mask layer to define a floating gate in said first polysilicon layer; oxidizing said first polysilicon layer; removing said mask layer; etching said first polysilicon layer to form said floating gate; depositing a tunnel oxide layer over said first polysilicon layer; depositing a silicon nitride layer over said tunnel oxide layer; depositing a tetraethyl orthosilicate (TEOS) layer over said silicon nitride layer; performing anisotropic etch of said TEOS layer and said silicon nitride layer to form multi-layer spacer (MLS); forming source and drain regions in said substrate using said MLS for alignment; depositing an interpoly oxide layer over said substrate; forming a second polysilicon layer over said interpoly oxide layer; and patterning said second polysilicon layer to form a control gate and complete said flash EEPROM cell.